Collaborate
For once, you don?t have to listen to your professor as you are free to fuse the die-hard electronic genius in you with the chips and the micro-processors provided. This is one place where you can show exactly what you are made of, chip by chip!!
Event Structure
- This is a single phase event.
- Problem will be given on the spot.
- Solving problem consist of making Pseudo Code and then writing its code using verilog.
- Then implementing this code on F.P.G.A.
Rules
- Workshop is not mandatory.
- Problem statement: During the event
- Team size: 1-3
- Weightage:
- Psuedo code : 20%
- Verilog : 40%
- FPGA Implementation : 20%
- Efficiency of design: 20%
- Time limit: not exceedable
- Any form of reference material IF NOT DIGITAL is allowed.
- Decision of Judges will be final.
Contact
Sagar Aswani - 200701132@daiict.ac.in
Prabhat Sachan - 200701139@daiict.ac.in
Anup Kumar - 200701193@daiict.ac.in
